1. Field of the Invention
The present invention relates to a layered chip package that includes a plurality of semiconductor chips stacked, and to a method of manufacturing the same.
2. Description of the Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips; has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation.
The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; filling the plurality of holes with metal such as Cu by plating to form the through electrodes; and removing unwanted portions of the seed layer.
According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal. This tends to reduce the reliability of wiring formed by the through electrodes.
According to the through electrode method, vertically adjacent chips are physically joined to each other by connecting the through electrodes of the upper chip and those of the lower chip by soldering, for example. The through electrode method therefore requires that the vertically adjacent chips be accurately aligned and then joined to each other at high temperatures. When the vertically adjacent chips are joined to each other at high temperatures, however, misalignment between the vertically adjacent chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the vertically adjacent chips.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
The manufacturing method disclosed in U.S. Pat. No. 5,953,588 requires a large number of steps and this raises the cost for the layered chip package. According to the method, after a plurality of chips cut out from a processed wafer are embedded into the embedding resin, a plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.
With the multilayer module disclosed in U.S. Pat. No. 7,127,807 B2, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration.
U.S. Pat. Nos. 7,863,095 B2 and 7,868,442 B2 each describe a layered chip package having a configuration as described below and its manufacturing method. The layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions that are stacked. Each of the plurality of layer portions includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface with a device formed thereon, and a second surface opposite to the first surface. The plurality of electrodes are connected to the semiconductor chip. Each of the plurality of electrodes has an end face located in the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions. The plurality of layer portions include at least a pair of layer portions that are arranged so that the first surfaces of the respective semiconductor chips face each other.
In the method of manufacturing the layered chip package disclosed in U.S. Pat. Nos. 7,863,095 B2 and 7,868,442 B2, first and second pre-polishing substructures are fabricated. Each of the first and second pre-polishing substructures has a first surface and a second surface, and includes a plurality of pre-semiconductor-chip portions that are arrayed. The first and second pre-polishing substructures are bonded to each other with their respective first surfaces arranged to face each other, and then their respective second surfaces are polished to fabricate a layered substructure including first and second substructures. The layered substructure is used to form a plurality of layered chip packages. Such a manufacturing method allows the substructures to be easily reduced in thickness while preventing damage to the substructures, and also allows the substructures to be handled easily. This makes it possible to manufacture a compact and highly integrated layered chip package with a high yield.
However, in the layered chip package and its manufacturing method disclosed in U.S. Pat. Nos. 7,863,095 and 7,868,442, the electrodes in two layer portions making up a pair are arranged in different layouts. This is one factor that increases the cost of the layered chip package.